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LOGIC Devices Introduces Industry's Highest Density FIFO / Frame Buffer

24Mbit Memory Addresses Complex Data Buffering Applications with Random Access Capabilities

SUNNYVALE, Calif., - March 10, 2005
LOGIC Devices (Nasdaq: LOGC), a developer of high performance application specific integrated circuits, today announced it has begun sampling its next-generation LF3324 Frame Buffer / FIFO. The device leads the industry in density and flexibility by integrating 24Mbit memory with robust addressing capabilities including both sequential and random access modes. This integrated approach simplifies video and data buffering systems that typically use standard Random Access Memories (RAM) paired with Field Programmable Gate Array (FPGA) logic.

The new LF3324 features independent input and output data ports along with several addressing modes. The 24Mbit memory can be accessed sequentially, through random access, or both. Flexible addressing modes allow the device to perform First-In First-Out (FIFO), Shift Register and mixed Sequential/Random Access functions. With a maximum data rate of 74MHz, the LF3324 is well positioned to buffer multiple video formats, including HDTV. Devices can be cascaded to enable even larger word-widths or depths. A seamless address space is maintained in the Random Access mode, even when cascading multiple devices for high-resolution images. The Input/Output ports are capable of accepting 8, 10 or 12 bit data without wasting memory.

LOGIC Devices' new offering is targeted at broadcast video equipment, medical imaging, machine vision, video editing systems and security surveillance applications. The device configurability, along with its 74MHz operating speed, provides the designer with unprecedented flexibility in applications requiring storage density, speed, and flexible addressing. The Random Access modes facilitate complex addressing schemes such as multi-queue buffering, image rotation, video compression algorithms, area of interest (AOI) and picture in picture (PIP) extraction. The FIFO and Shift Register modes are useful in synchronizing multiple video streams or data feeds, frame synchronization, motion detection, scan rate conversion, motion adaptive de-interlacing, and time base correction (TBC).

The LF3324 is packaged in a 15mm x 15mm small form factor 172-pin Low Profile Ball Grid Array (LBGA) package. The package will be available in a Green version, which meets the joint IPC/JEDEC standard J-STD-020B and complies with European Union requirements scheduled to take effect in 2006.

Pricing and Availability

Commercial temperature grade samples of the LF3324 are immediately available. Production quantities will be available in the fourth calendar quarter of 2005. Initial pricing for the LF3324 is $37 each in quantities of 10,000. Information including the complete datasheet, application notes, and package drawings are available online on the LF3324 page. Print-quality photos for news release purposes are available at LF3324 Photos

About LOGIC
LOGIC Devices Incorporated (Nasdaq: LOGC) is focused on developing high performance digital integrated circuits for applications requiring high-density embedded memory, high speed and low power consumption. LOGIC Devices’ product solutions meet the requirements of leading broadcast video, medical imaging, surveillance, instrumentation, and telecommunications companies.

Editorial Contact:
Adam Scraba
Product Marketing Manager
(408) 542-5415
LOGIC Devices Incorporated
adam@logicdevices.com

 
 
   
   
   
   
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