The LF3312 is a 12,441,600 bit memory device with extremely flexible addressing capabilities along with seamless cascadability. The device's feature-set makes it ideal for DTV, HDTV, Security, Medical Imaging, Machine Vision, and Broadcast Video buffering systems. Word widths of 8, 10, and 12bits are supported.

		Independent Write/Read Pointer Manipulation
		Multiple FIFO and Shift Register sequential-addressing Modes
		Full-time Random Access address control
		Allocate Multiple Regions in Memory for Multi-frame, Multi-queue, PIP solutions
		74.25MHz Max Data Rate
		2 or 4 I/O Ports for Dual or Single Channel Buffering
		Built-in ITU-R BT. 656 TRS Detection and Synchronization
		Seamless Address space when cascading multiple devices (up to 16 devices)
		8, 10, 12, 16, 20, or 24bit Data Access without Wasting Memory
		Pb-Free Packaging (Full Green)

Part Number Package Mechanical Drawing BSDL File (5/17/05) LF3312BGC 172 ball LBGA BG1 LF3312_bsdl.zip

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