Legacy Product Technical Documents
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  LMU112 - 12 x 12-bit Parallel Multiplier  
Features
  • 25 ns Worst-Case Multiply Time
  • Low Power CMOS Technology
  • Replaces Fairchild MPY112K
  • Two's Complement or Unsigned Operands
  • Three-State Outputs
  • Package Styles Available:
    • 48-pin PDIP
    • 52-pin PLCC, J-Lead

For more INFORMATION: 1-408-542-5400 or

Part Number Package Mechanical Drawing
LMU112JC25
LMU112JC50
Plastic J-Lead Chip Carrier 52-pins J5
LMU112PC25
LMU112PC50
Plastic DIP 48-pins P5
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Resources
· Download Datasheet
· View Block Diagram
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